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SPT
SIGNAL PROCESSING TECHNOLOGIES
SPT7760
8-BIT, 1 GSPS FLASH A/D CONVERTER
APPLICATIONS
* * * * Digital Oscilloscopes Transient Capture Radar, EW, ECM Direct RF Down-Conversion
FEATURES
* * * * * * 1:2 Demuxed ECL Compatible Outputs Wide Input Bandwidth - 900 MHz Low Input Capacitance - 15 pF (MQUAD) Metastable Errors Reduced to 1 LSB Monolithic for Low Cost Gray Code Output
GENERAL DESCRIPTION
The SPT7760 is a full parallel (flash) analog-to-digital converter capable of digitizing full scale (0 to -2 V) inputs into eight-bit digital words at an update rate of 1 GSPS. The ECLcompatible outputs are demultiplexed into two separate output banks, each with differential data ready outputs to ease the task of data capture. The SPT7760's wide input bandwidth and low capacitance eliminate the need for external track-and-hold amplifiers for most applications. A propriCLK CLK
etary decoding scheme reduces metastable errors to the 1 LSB level. The SPT7760 operates from a single -5.2 V supply, with a nominal power dissipation of 5.5 W. The SPT7760 is available in an 80L surface-mount MQUAD package over the industrial temperature range. Contact the factory for availability of die and /883 versions.
BLOCK DIAGRAM
Analog V RT Input Preamp Comparator 256
CLOCK BUFFER DEMUX CLOCK BUFFER
255
D8 (OVR)
D8B D7B * * D5B * * D2B
152
256 TO 8 BIT DECODER WITH METASTABLE ERROR CORRECTION
D7 (MSB) D6
151
D5
1:2 DEMULTIPLEXER
128
D1B D0B D8A D7A * * * D5A * * * D2A D1A D0A
VRM
127
D4
64
D3
63
D2
2
D1
DRB (DATA READY) DRB (DATA READY) D8B (OVR) D7B (MSB) D6B D5B D4B D3B D2B D1B D0B (LSB) DRA (DATA READY) DRA (DATA READY) D8A (OVR) D7A (MSB) D6A D5A D4A D3A D2A D1A D0A (LSB)
1
DO (LSB)
VRB
Signal Processing Technologies, Inc.
4755 Forge Road, Colorado Springs, Colorado 80907, USA Phone: (719) 528-2300 FAX: (719) 528-2370 Website: http://www.spt.com E-Mail: sales@spt.com
ECL OUTPUT BUFFERS AND LATCHES
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 C
Supply Voltages Negative Supply Voltage (VEE TO GND) ......... .-7.0 to +0.5 V Ground Voltage Differential ............................. .-0.5 to +0.5 V Input Voltage Analog Input Voltage ........................................ +0.5 V to VEE Reference Input Voltage .................................. +0.5 V to VEE Digital Input Voltage ......................................... +0.5 V to VEE Reference Current VRT to VRB .................................... 35 mA Output Digital Output Current ........................................ 0 to -28 mA Temperature Operating Temperature, ambient ...................... .-25 to +85 C case ................................... +125 C junction ............................... +150 C Lead Temperature, (soldering 10 seconds). ............. +300 C Storage Temperature ...................................... -65 to +150 C
Notes: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications.
ELECTRICAL SPECIFICATIONS
TJ = TC = TA = +25 C , VEE=-5.2 V, VRB=-2.00 V, VRM=-1.0 V, VRT=0.00 V, fclk=1 GHz, Duty Cycle=50%, unless otherwise specified.
PARAMETERS Resolution DC Accuracy (+25 C) Integral Nonlinearity Differential Nonlinearity No Missing Codes Analog Input Input Voltage Range Input Bias Current Input Resistance Input Capacitance Input Bandwidth Small Signal Large Signal Offset Error VRT Offset Error VRB Input Slew Rate Clock Synchronous Input Currents Reference Input Ladder Resistance Reference Bandwidth Timing Characteristics Maximum Sample Rate Aperture Jitter Acquisition Time CLK to Data Ready Delay Clock to Data Delay Dynamic Performance Signal-To-Noise Ratio (without Harmonics) fIN = 50 MHz fIN = 250 MHz Total Harmonic Distortion fIN = 50 MHz fIN = 250 MHz
TEST CONDITIONS
TEST LEVEL
MIN
SPT7760A TYP MAX 8
MIN
SPT7760B TYP MAX UNITS 8 Bits
fCLK = 100 kHz fCLK = 100 kHz
I I
-1.0 -0.85 Guaranteed
+1.0 +0.95
-1.5 -0.95
+1.5 LSB +1.5 LSB Guaranteed VRT V 2.0 mA k pF MHz MHz +30 mV +30 mV V/ns A 80 30 MHz GHz ps ps 1.9 ns 2.25 ns
VIN=0 V Over Full Input Range
I I V V V V I I V V I V I V V IV IV
VRB .75 15 15 900 500 -30 -30 5 2 60 80 30
VRT 2.0
VRB .75 15 15 900 500
+30 +30
-30 -30 5 2 60
1 2 250 1.4 1.75
1 2 250 1.4 1.75
0.9 1.25
1.9 2.25
0.9 1.25
I I I I
45 43 -44 -36
43 41 -42 -34
dB dB dBc dBc
SPT
SPT7760
2
3/10/97
ELECTRICAL SPECIFICATIONS
TJ = TC = TA = +25 C , VEE=-5.2 V, VRB=-2.00 V, VRM=-1.0 V, VRT=0.00 V, fclk=1 GHz, Duty Cycle=50%, unless otherwise specified.
PARAMETERS Dynamic Performance Signal-to-Noise and Distortion fIN = 50 MHz fIN = 250 MHz Spurious Free Dynamic Range fIN = 50 MHz fIN = 250 MHz Digital Inputs Input High Voltage (CLK, NCLK) Input Low Voltage (CLK, NCLK) Clock Pulse Width High (tPWH) Clock Pulse Width Low (tPWL) Digital Outputs Logic "1" Voltage Logic "0" Voltage Rise Time Fall Time Power Supply Requirements Voltage VEE Current IEE Power Dissipation
TEST CONDITIONS
TEST LEVEL
MIN
SPT7760A TYP MAX
MIN
SPT7760B TYP MAX UNITS
I I I I
42 35 47 39
40 33 43 35
dB dB dB dB
I I I I I I V V IV I I
-1.1
-0.7 -1.8 0.4 0.4 -0.9 -1.8 450 450 -5.2 1.05 5.5 -1.5
-1.1
-0.7 -1.8 0.4 0.4 -0.9 -1.8 450 450 -5.2 1.05 5.5
V -1.5 V ns ns V -1.5 V ps ps -5.45 V 1.2 A 6.25 W
0.5 0.5 -1.1
0.5 0.5 -1.1 -1.5
20% to 80% 20% to 80%
-4.95
-5.45 1.2 6.25
-4.95
Typical Thermal Impedance: JC = +4 C/W.
TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition. Unless otherwise noted, all tests are pulsed tests; therefore, TJ = TC = TA.
TEST LEVEL I II III IV V VI
TEST PROCEDURE 100% production tested at the specified temperature. 100% production tested at TA=25 C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = 25 C. Parameter is guaranteed over specified temperature range.
SPT
SPT7760
3
3/10/97
GENERAL DESCRIPTION
The SPT7760 is the fastest monolithic 8-bit parallel flash A/D converter available today. The nominal conversion rate is 1 GSPS and the analog bandwidth is in excess of 900 MHz. A major advance over previous flash converters is the inclusion of 256 input preamplifiers between the reference ladder and input comparators (see block diagram). This not only reduces clock transient kickback to the input and reference ladder due to a low AC beta but also reduces the effect of the dynamic state of the input signal on the latching characteristics of the input comparators. The preamplifiers act as buffers and stabilize the input capacitance so that it remains constant over different input voltage
and frequency ranges and therefore makes the part easier to drive than previous flash converters. The preamplifiers also add a gain of two to the input signal so that each comparator has a wider overdrive or threshold range to "trip" into or out of the active state. This gain reduces metastable states that can cause errors at the output. The SPT7760 has true differential analog and digital data paths from the preamplifiers to the output buffers (Current Mode Logic) for reducing potential missing codes while rejecting common mode noise. Signature errors are also reduced by careful layout of the analog circuitry. The output drive capability of the device can provide full ECL swings into 50 loads.
Figure 1 - SPT7760 Typical Interface Circuit
DRB DRB DRA
50
DRB (DATA READY) U3 DRB (DATA READY) DRA (DATA READY) U3
50
VIN** 50
VIN VIN
DRA
DRA (DATA READY) -2.0 V Pulldown (Digital)
VRTF R 22 VRM VRTS
D8B (OVR) D7B (MSB) D6B D5B D4B D3B D2B D1B D0B (LSB)
+ U1 R
*
22 2N2907
U1
VRBS VRBF
-2.0 V Reference
*
50
D8A (OVR) D7A (MSB) D6A D5A D4A D3A D2A D1A D0A (LSB)
50
Convert
U2
AGND
DGND
VEE
SPT
+ -
-5.2 V
-5.2 V
CLK NCLK 50 50 FB = Ferrite bead
.1 F
-2.0 V Pulldown (Digital)
U1 = OP291 or equivalent with low offset/noise. R = 1 k; 0.1% matched. = AGND = DGND U2 = Motorola ECLinPS Lite, MC10EL16, differential receiver. U3 = MC10EL16 OR MC100EL16. * = 10 F Tantalum Capacitor and 0.1 F Chip Capacitor
-2 V Pulldown (Analog) -5.2 V
*
FB
** = Care must be taken to avoid exceeding the maximum rating for the input, especially during power up sequencing of the analog input driver.
SPT7760
4
3/10/97
TYPICAL INTERFACE CIRCUIT
The circuit in figure 1 is intended to show the most elaborate method of achieving the least error by correcting for integral linearity, input induced distortion and power supply/ground noise. This is achieved by the use of external reference ladder tap connections, input buffer and supply decoupling. Please contact the factory for the SPT7760 evaluation board applications note that contains more details on interfacing the SPT7760. The function of each pin and external connections to other components is as follows: VEE, AGND, DGND VEE is the supply pin with AGND as ground for the device. The power supply pins should be bypassed as close to the device as possible with at least a .01 F ceramic capacitor. A 1 F tantalum can also be used for low frequency suppression. DGND is the ground for the ECL outputs and is to be referenced to the output pulldown voltage and appropriately bypassed as shown in figure 5. VIN (ANALOG INPUT) There are two analog input pins that are tied to the same point internally. Either one may be used as an analog input sense and the other for input force. This is convenient for testing the source signal to see if there is sufficient drive capability. The pins can also be tied together and driven by the same source. The SPT7760 is superior to similar devices due to a preamplifier stage before the comparators. This makes the device easier to drive because it has constant capacitance and induces less slew rate distortion. CLK, CLK (CLOCK INPUTS) The clock inputs are designed to be driven differentially with ECL levels. The duty cycle of the clock should be kept at 50% to avoid causing larger second harmonics. If this is not important to the intended application, then duty cycles other than 50% may be used. D0 TO D8, DR, NDR (A AND B) The digital outputs can drive 50 to ECL levels when pulled down to -2 V. When pulled down to -5.2 V, the outputs can drive 130 to 1 k loads. All digital outputs are grey code with the coding as shown in table 1. SPT recommends using differential receivers on the outputs of the data ready lines to ensure the proper output rise and fall times. VRBF, VRBS, VRTF, VRTS, VRM (REFERENCE INPUTS) There are two reference inputs and one external reference voltage tap. These are -2 V (VRB force and sense), mid-tap
(VRM) and AGND (VRT force and sense). The reference pins and tap can be driven by op amps as shown in figure 1 or VRM may be bypassed for limited temperature operation. These voltage inputs can be bypassed to AGND for further noise suppression if so desired. Table I - Output Coding
VIN > -0.5 LSB -0.5 LSB D8 D7 * * * D0 1 1 0 0 0 * * * 0 0 * * * 0 0 0 10000000 10000000 10000000 10000000 10000001 * * * 11000000 01000000 * * * 00000001 00000000 00000000
-1.5 LSB
* * * -1.0 V
* * * -2.0 V+ 1/2 LSB
< (-2.0 V +1/2 LSB)
Indicates the transition between the two codes
THERMAL MANAGEMENT The typical thermal impedance has been measured as follows: CA = +17 C/W in still air with no heat sink We highly recommend that a heat sink be used for this device with adequate air flow to ensure rated performance of the device. We have found that a Thermalloy 17846 heat sink with a minimum air flow of 1 meter/second (200 linear feet per minute) provides adequate thermal performance under laboratory tests. Application specific conditions should be taken into account to ensure that the device is properly heat sinked.
SPT
SPT7760
5
3/10/97
OPERATION
The SPT7760 has 256 preamp/comparator pairs which are each supplied with the voltage from VRT to VRB divided equally by the resistive ladder as shown in the block diagram. This voltage is applied to the positive input of each preamplifier/comparator pair. An analog input voltage applied at VIN is connected to the negative inputs of each preamplifier/comparator pair. The comparators are then clocked through each one's individual clock buffer. When the CLK pin is in the low state, the master or input stage of the comparators compare the analog input voltage to the respective reference voltage. When the CLK pin changes from low to high the comparators
are latched to the state prior to the clock transition and output logic codes in sequence from the top comparators, closest to VRT (0 V), down to the point where the magnitude of the input signal changes sign (thermometer code). The output of each comparator is then registered into four 64-to-6 bit decoders when the CLK is changed from high to low. At the output of the decoders is a set of four 7-bit latches which are enabled ("track") when the clock changes from high to low. From here, the output of the latches are coded into 6 LSBs from 4 columns and 4 columns are coded into 2 MSBs. Finally, 8 ECL output latches and buffers are used to drive the external loads. The conversion takes one clock cycle from the input to the data outputs.
Figure 2 - Timing Diagram
VIN
N
N+1 N+2 1.0 ns N+3 N+4
N+5
N+6 N+7
CLK NCLK
1.4 ns typ
DRA NDRA N-2
1.75 ns typ
Data Bank A
N
N+2
N+4
DRB NDRB
1.4 ns typ
Data Bank B
N-1
1.75 ns typ
N+1
N+3
Figure 3 - Subcircuit Schematics INPUT CIRCUIT
AGND
OUTPUT CIRCUIT
AGND DGND
CLK
CLOCK INPUT
AGND
VIN
VR
CLK
Data Out
VEE
VEE
SPT
SPT7760
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3/10/97
PACKAGE OUTLINES
80-PIN MQUAD
H
INCHES MILLIMETERS MIN 23.80 19.72 12.0 TYP 13.73 17.80 0.80 TYP 0.36 TYP 2.90 0.15 TYP 18.4 TYP 0.109 0.036 2.51 7 0.66 2.77 0.91 MAX 24.00 19.93 13.94 18.00 0.945 0.785 0.549 0.709
F
G
I
SYMBOL A B C D E F G H
MIN 0.937 0.777 0.472 TYP 0.541 0.701 0.032 TYP 0.014 TYP 0.114 .006 TYP 0.724 TYP 0.099 7 0.026
MAX
0.122
3.10
A
B
J
I J K L M
M C D E K L
SPT
SPT7760
7
3/10/97
PIN ASSIGNMENTS
D4A D5A V EE D6A DGND D7A DGND D8A DGND NDRB DGND DRB DGND DOB V EE D1B 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
PIN FUNCTIONS
Name VEE AGND VRTF VRTS VRM VRBF VRBS VIN DGND D0-D7A D0-D7B DRA NDRA DRB NDRB D8A D8B CLK NCLK Function Negative Supply Nominally -5.2 V Analog Ground Reference Voltage Force Top, Nominally 0 V Reference Voltage Sense Top Reference Voltage Middle, Nominally -1 V Reference Voltage Force Bottom, Nominally -2 V Reference Voltage Sense Bottom Analog Input Voltage, Can Be Either Voltage or Sense Digital Ground Data Output Bank A Data Output Bank B Data Ready Bank A Not Data Ready Bank A Data Ready Bank B Not Data Ready Bank B Overrange Output Bank A Overrange Output Bank B Clock Input Clock Input
D2B D3B D4B V EE V EE D5B DGND D6B DGND D7B DGND D8B N/C N/C AGND AGND AGND AGND V EE V EE V RBF V EE V EE V RBS
1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 16 17 18 19 20 21 22 23 24
MQUAD
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
N/C N/C D3A D2A V EE D1A DGND DOA DGND NDRA DGND DRA AGND AGND CLK V EE NCLK V EE V EE AGND AGND V RTS V RTF N/C
ORDERING INFORMATION
PART NUMBER
SPT7760AIK SPT7760BIK
Signal Processing Technologies, Inc. reserves the right to change products and specifications without notice. Permission is hereby expressly granted to copy this literature for informational purposes only. Copying this material for any other use is strictly prohibited. WARNING - LIFE SUPPORT APPLICATIONS POLICY - SPT products should not be used within Life Support Systems without the specific written consent of SPT. A Life Support System is a product or system intended to support or sustain life which, if it fails, can be reasonably expected to result in significant personal injury or death. Signal Processing Technologies believes that ultrasonic cleaning of its products may damage the wire bonding, leading to device failure. It is therefore not recommended, and exposure of a device to such a process will void the product warranty.
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 V EE V EE AGND AGND V IN V IN N/C AGND AGND
DESCRIPTION
INL = 1.0 LSB INL = 1.5 LSB
V EE V EE V EE AGND AGND V RM N/C
PACKAGE TYPE
80L MQUAD 80L MQUAD
TEMPERATURE RANGE
-25 to +85 C -25 to +85 C
SPT
SPT7760
8
3/10/97

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